[vlsi-nastava:2003] - Wishbone by "Zarko Acimovic" <zareac@galeb.etf.bg.ac.yu>

Imam jedno pitanje u vezi Wishbone specifikacije kada se radi o SINGLE WRITE Cycle.  Naime SLAVE kao odgovor na aktivnosti MASTER-a postavlja ACK_I, a potom se priprema da latch-uje podatke na [DAT_O()] . Da li je ovaj [DAT_O()] od MASTER-a, pa onda SLAVE treba da latch-uje te podatke koje je MASTER izbacio? Meni se cini da jeste, ali to nije bas precizno receno, pa me malo zbunjuje.

Hvala, Zare

3.2.2 SINGLE WRITE Cycle

CLOCK EDGE 0: MASTER presents [ADR_O()] and [TAGN_O].

MASTER asserts [WE_O] to indicate a WRITE cycle.

MASTER presents bank select [SEL_O()] to indicate where it sends data.

MASTER asserts [CYC_O] to indicate the start of the cycle.

MASTER asserts [STB_O] to qualify [ADR_O()], [SEL_O()] and [WE_O].



SETUP, EDGE 1: SLAVE decides inputs, and responds by asserting [ACK_I].

SLAVE presents prepares to latch data on [DAT_O()].

SLAVE asserts [ACK_I] in response to [STB_O] to indicate latched data.

SLAVE presents [TAGN_O].

MASTER monitors [TAGN_I].

MASTER monitors [ACK_I], and prepares to terminate the cycle.

Note: SLAVE may insert wait states (-WSS-) before asserting [ACK_I],

thereby allowing it to throttle the cycle speed. Any number of wait states

may be added.

CLOCK EDGE 1: SLAVE latches data on [DAT_O()].

MASTER latches [TAGN_I].