[vlsi-nastava:2005] - arbitrator magistrale - resenje by Gvozden Marinkovic <mgvozden@eunet.yu>

entity arbiter is
	port (
		clk: in bit;
		rst: in bit;
		request: in bit_vector(0 to 3);
		ack: out bit_vector(0 to 3)
	);
end entity arbiter;				

architecture beh of arbiter is
	type states is (FREE, BUSY);
	signal state, next_state: states;
	signal index: natural range 0 to 3;
begin			
	change_state: process(rst, clk) is
	begin
		if rst = '1' then
			state <= FREE;
		elsif clk'event and clk = '1' then
			state <= next_state;
		end if;
	end process change_state;				
	
	calc_next_state: process (state, request, index) is
	begin	
		case state is
			when FREE =>
				next_state <= FREE;
				if request(index) = '1' then
					next_state <= BUSY;
				end if;				
			when BUSY =>
				next_state <= BUSY;
				if request(index) = '0' then
					next_state <= FREE;
				end if;				
		end case;
	end process calc_next_state;
	
	set_signals: process (rst, clk) is
	begin			
		if rst = '1' then				
			index <= 0;			
			ack <= (others => '0');
		elsif clk'event and clk='1' then
			case next_state is
				when FREE =>
					ack <= (others => '0');
					index <= (index + 1) mod 4;
				when BUSY =>
					ack(index) <= '1';
			end case;
		end if;
	end process set_signals;
end architecture beh;