problem u Active-HDL 6.2
Imam sledeci problem:
imam e1_deframer.vhd koji predstavlja blok e1 deframera sa slike iz teksta
zadatka
i u okviru njega registar_13, koju sam opisao u registar_13.vhd
-- deo koda iz e1_deframer.vhd koja se tice registar_13
registar_13: entity work.registar_13(registar_13)
port map(Load => Load_Output_Register,
Reset => Reset,
Clk => Clk,
DataIN(12 downto 8) => Broj_Slota,
DataIN(7 downto 0) => bajt_Podataka,
DataOUT(12 downto 8) => Sn,
DataOUT(7 downto 0) => Data
);
--definicija entiteta iz registar_13.vhd
entity registar_13 is
port(
Load : in STD_LOGIC;
Reset : in STD_LOGIC;
Clk : in STD_LOGIC;
DataIN : in STD_LOGIC_VECTOR(12 downto 0);
DataOUT : out STD_LOGIC_VECTOR(12 downto 0)
);
end registar_13;
compile all prodje za sve fajlove, i analise svakog vhd fajla prodje osim za
e1_deframer.vhd
tu mi javlja gresku
# Family : Xilinx6x XPro_Virtex_Rad_Hard is not supported
# Family : Xilinx6x XPro_Virtex_Hi_Rel is not supported
# Family : Xilinx6x VIRTEX is not supported
# Analysis in progress. Please wait...
# fff rev_1
# $ Start of Compile
# #Mon Aug 22 17:00:46 2005
# Synplicity VHDL Compiler, version Compilers 2.8.1, Build 015R, built Sep 2
2004
# Copyright (C) 1994-2004, Synplicity Inc. All Rights Reserved
# @N:"C:\My_Designs\rade\e1_deframer\src\e1_deframer1.vhd":30:7:30:18|Top
entity
is set to e1_deframer1.
# Error: Instantiated entity registar_13 has not been analyzed
# @E: CD415
:"C:\My_Designs\rade\e1_deframer\src\e1_deframer1.vhd":73:32:73:32|Expecting
keyword is
# @E: CD319
:"C:\My_Designs\rade\e1_deframer\src\e1_deframer1.vhd":81:26:81:26|duplicate
design unit name work
# @E: CD319
:"C:\My_Designs\rade\e1_deframer\src\e1_deframer1.vhd":90:24:90:24|duplicate
design unit name work
# @E: CD319
:"C:\My_Designs\rade\e1_deframer\src\e1_deframer1.vhd":97:20:97:20|duplicate
design unit name work
# 5 errors parsing file C:\My_Designs\rade\e1_deframer\src\e1_deframer1.vhd
# @END
# Process took 0h:0m:0s realtime, 0h:0m:0s cputime
# Analysis status: 1 errors, 0 warnings
ima li neko ideju sta moze biti problem, zaglavih se ovde ceo dan
pozdrav, rade
imam e1_deframer.vhd koji predstavlja blok e1 deframera sa slike iz teksta
zadatka
i u okviru njega registar_13, koju sam opisao u registar_13.vhd
-- deo koda iz e1_deframer.vhd koja se tice registar_13
registar_13: entity work.registar_13(registar_13)
port map(Load => Load_Output_Register,
Reset => Reset,
Clk => Clk,
DataIN(12 downto 8) => Broj_Slota,
DataIN(7 downto 0) => bajt_Podataka,
DataOUT(12 downto 8) => Sn,
DataOUT(7 downto 0) => Data
);
--definicija entiteta iz registar_13.vhd
entity registar_13 is
port(
Load : in STD_LOGIC;
Reset : in STD_LOGIC;
Clk : in STD_LOGIC;
DataIN : in STD_LOGIC_VECTOR(12 downto 0);
DataOUT : out STD_LOGIC_VECTOR(12 downto 0)
);
end registar_13;
compile all prodje za sve fajlove, i analise svakog vhd fajla prodje osim za
e1_deframer.vhd
tu mi javlja gresku
# Family : Xilinx6x XPro_Virtex_Rad_Hard is not supported
# Family : Xilinx6x XPro_Virtex_Hi_Rel is not supported
# Family : Xilinx6x VIRTEX is not supported
# Analysis in progress. Please wait...
# fff rev_1
# $ Start of Compile
# #Mon Aug 22 17:00:46 2005
# Synplicity VHDL Compiler, version Compilers 2.8.1, Build 015R, built Sep 2
2004
# Copyright (C) 1994-2004, Synplicity Inc. All Rights Reserved
# @N:"C:\My_Designs\rade\e1_deframer\src\e1_deframer1.vhd":30:7:30:18|Top
entity
is set to e1_deframer1.
# Error: Instantiated entity registar_13 has not been analyzed
# @E: CD415
:"C:\My_Designs\rade\e1_deframer\src\e1_deframer1.vhd":73:32:73:32|Expecting
keyword is
# @E: CD319
:"C:\My_Designs\rade\e1_deframer\src\e1_deframer1.vhd":81:26:81:26|duplicate
design unit name work
# @E: CD319
:"C:\My_Designs\rade\e1_deframer\src\e1_deframer1.vhd":90:24:90:24|duplicate
design unit name work
# @E: CD319
:"C:\My_Designs\rade\e1_deframer\src\e1_deframer1.vhd":97:20:97:20|duplicate
design unit name work
# 5 errors parsing file C:\My_Designs\rade\e1_deframer\src\e1_deframer1.vhd
# @END
# Process took 0h:0m:0s realtime, 0h:0m:0s cputime
# Analysis status: 1 errors, 0 warnings
ima li neko ideju sta moze biti problem, zaglavih se ovde ceo dan
pozdrav, rade
- Follow-Ups:
- Re: problem u Active-HDL 6.2
- From: Vladimir Jokovic <joksa2000@yahoo.com>
- Re: problem u Active-HDL 6.2
- References:
- Pitanje za asistenta
- From: "jolly" <milimojkv@ptt.yu>
- Re: Pitanje za asistenta
- From: Gvozden Marinkovic <mgvozden@EUnet.yu>
- Pitanje za asistenta
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