[vlsi-nastava:2006] - Pitanje za Wishbone specifikaciju by "Igor Stojkovic" <stojkovic.igor@gmail.com>

RULE 3.110
SLAVE interfaces MUST be designed so that the [ACK_O], [ERR_O] and
[RTY_O] signals are asserted and negated in response to the assertion
and negation of [STB_I]. Furthermore, this activity MUST occur
asynchronous to the [CLK_I] signal (i.e. there is a combinatorial
logic path between [STB_I] and [ACK_O], etc.).

RULE 4.10
The clock input [CLK_I] to each IP core MUST coordinate all activities
for the internal logic within the WISHBONE interface. All WISHBONE
output signals are registered at the risingedge of [CLK_I]. All
WISHBONE input signals must be stable before the rising edge of
[CLK_I].

Kako to da ova dva pravila (a i drugo samo sa sobom) nisu u kontradiktornosti?

Prvo pravilo kaze da ACK_O mora da se postavi asinhrono sa CLK_I a
drugo kaze da se svi izlazni signali registruju(?) na rastucu ivicu
CLK_I.

Dodatno se u drugom pravilu kaze da svi ulazni signali moraju biti
stabilni pre rastuce ivice CLK_I. To mi s obzirom na prethodno u istom
pravilu, zvuci logicno jedino ako se misli da se na neku rastucu ivicu
postavljaju izlazni signali a oni treba da se detektuju (tj. da budu
stabilni na prijemnoj strani) posle tog trenutka ali pre sledece
rastuce ivice, jer i uredjaj na drugoj strani ima isti CLK.


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Pozdrav,
Igor Stojkovic mailto: stojkovic.igor@gmail.com