[vlsi-nastava:2007] - Re: pitanje za asistenta by Nenad Tesovic <tesovicn@gmail.com>

Sasa Stojanovic wrote:
> > Master reaguje SAMO na uzlaznu ivicu takta.
> > Slave reaguje SAMO na silaznu ivicu takta.
> wbspec_b1, strana 56, pravilo 4.10.

RULE 4.10
The clock input [CLK_I] to each IP core MUST coordinate all activities 
for the internal logic within the WISHBONE interface. All WISHBONE 
output signals are registered at the rising edge of [CLK_I]. All 
WISHBONE input signals must be stable before the rising edge of [CLK_I].

Ja ne vidim da se ovde pominje silazna ivica, niti se pominju master i 
slave?
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