[vlsi-nastava:2007] - Re: Za kolegu koji je pitao za procese... by "Veljko M" <mightymv@gmail.com>

Hvala, kolega, vidim budni smo i VREDNI do sitnih sati.  :))
> 2007/6/23, Aleksandar Crnjin <acrnjin@gmail.com>:
> >
> > Nasao sam ovo u Xilinx Design Guidelines:
> >
> > Filling out a Process Sensitivity List
> >
> > ·          Within a combinatorial process, all signals that are read
> > (which can change) must be in the sensitivity list.
> >
> > ·          This will insure the correct behavioral simulation.  This
> > includes any signals that are compared in if-then-else statements and case
> > statements.  It also includes any signal on the right-hand side of an
> > assignment operator. Remember that this is only for signals that can change.
> > A constant cannot change; thus, it does not need to be in the
> > sensitivity list.
> >
> > ·          Within a clocked process, only an asynchronous set or reset
> > and the clock should be in the sensitivity list.
> >
> > ·          If others are added, the functionality of a behavioral
> > simulation will still be correct. However, the simulation will be slower
> > because that process will need to be evaluated or simulated whenever a
> > signal in its sensitivity list changes.
> >
> > Tako da, po ovome ispada da je kolega bio u pravu (sa obzirom da se
> > promena desava samo na clk, ne treba navoditi ove ostale)
> >
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