[vlsi-nastava:2007] - Fwd: Predavanje iz arhitekture racunara, 20.9.2007@14h(26) by Sasa Stojanovic <stojsasa@yahoo.com>

Dr Veljko Milutinovic <vm@etf.bg.ac.yu> wrote:
 
Cetvrtak 20.9.2007 @14h (sala 26 u novom paviljonu "Rasovic")

Ronald Dreslinski, University of Michigan, Ann Arbor, MI, USA
(Ph.D.Student of Prof. Trevor Mudge):

An Energy Efficient Parallel Architecture Using Near Threshold Operation

Abstract

Subtreshold circuit design, while energy efficient, has the drawback of 
performance degradation. To retain the excellent energy efficiency while 
reducing performance loss, we propose to investige near subtreshold 
techniques on chip multiprocessors (CMP). We show that logic and memory 
cells have different optimal supply and treshold voltages; therefore, we 
propose to allow the cores and memory to operate in different voltage 
regions. With the memory operating at a different voltage, we then 
explore the design space in which several slower core clustered together 
share a faster L1 cache. We show that an architecture such as this is 
optimal for energy efficiency. In addition we explore the design 
tradeoffs that occur if we have separate instruction and data caches. 
We show that some applications prefer the data cache to be clustered, 
while the instruction cache is kept private to the core allowing further 
energy savings of a 77% reduction over a single core machine.


       
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