greska u quartus-u
Zdravo svima,
Da li je neko mozda imao istu gresku ili mozda zna resenje ovog problema...
Gledao sam u Quartus-ovom helpu i na internetu ali nisam nasao resenje.
Error: The node "operational_unit:unit_op|MAR:unit_MAR|O_tmp" has multiple drivers due to the constant driver
Evo ga i kod MAR-a:
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.std_match;
entity MAR is
generic (n: natural := 18);
port
(
I1 : in std_logic_vector (1 downto 0); -- PAGE bits
I0 : in std_logic_vector (n-3 downto 0); -- IBUS bits
clk : in std_logic;
ld : in std_logic;
inc : in std_logic;
en : in std_logic; -- enable tristate driver
O : out std_logic_vector (n-1 downto 0) -- out to ABUS
);
end MAR_new2;
architecture behaviour of MAR is
signal O_tmp : std_logic_vector (n-1 downto 0);
begin
process (clk)
begin
-- wait on clk's rising edge
if (clk'event and std_match(clk, '1')) then
if (std_match(ld, '1')) then
O_tmp(n-1 downto n-2) <= I1;
O_tmp(n-3 downto 0) <= I0;
end if;
if (std_match(inc, '1')) then
O_tmp <= O_tmp + '1';
end if; end if;
-- tristate driver
if (std_match(en, '1')) then
O <= O_tmp;
else
O <= (O'range => 'Z');
end if;
end process;
end behaviour;
Hvla unapred,
Nemanja
Da li je neko mozda imao istu gresku ili mozda zna resenje ovog problema...
Gledao sam u Quartus-ovom helpu i na internetu ali nisam nasao resenje.
Error: The node "operational_unit:unit_op|MAR:unit_MAR|O_tmp" has multiple drivers due to the constant driver
Evo ga i kod MAR-a:
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.std_match;
entity MAR is
generic (n: natural := 18);
port
(
I1 : in std_logic_vector (1 downto 0); -- PAGE bits
I0 : in std_logic_vector (n-3 downto 0); -- IBUS bits
clk : in std_logic;
ld : in std_logic;
inc : in std_logic;
en : in std_logic; -- enable tristate driver
O : out std_logic_vector (n-1 downto 0) -- out to ABUS
);
end MAR_new2;
architecture behaviour of MAR is
signal O_tmp : std_logic_vector (n-1 downto 0);
begin
process (clk)
begin
-- wait on clk's rising edge
if (clk'event and std_match(clk, '1')) then
if (std_match(ld, '1')) then
O_tmp(n-1 downto n-2) <= I1;
O_tmp(n-3 downto 0) <= I0;
end if;
if (std_match(inc, '1')) then
O_tmp <= O_tmp + '1';
end if; end if;
-- tristate driver
if (std_match(en, '1')) then
O <= O_tmp;
else
O <= (O'range => 'Z');
end if;
end process;
end behaviour;
Hvla unapred,
Nemanja
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