[vlsi-nastava:2009] - za asistenta - Memorija nece da cita sa adrese nula by Nemanja Ilic <nemanja.ilic.81@gmail.com>

Postovani,

Mi smo skoro zavrsili procesor, ostala je samo jedna stvar koja ne radi 
a to je da memorija nece da procita podatak sa adrese nula kada je u 
pitanju prekid zbog nelegalne instrukcije. Sa ostalih adresa cita i 
upisuje kako treba, to je testirano...
Molim za pomoc.

Unapred zahvalan
Nemanja Ilic
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.std_match;
--use ieee.numeric_std.all;

entity mem is
    generic (wdh : natural := 16;
             size : natural := 1024 * 256;
             lines : natural := 18;
             ctd : TIME := 10 ns -- clock cycle
            );
    port
    (
       clk       :   in std_logic;
       rst       :   in std_logic;
       rd        :   in std_logic;
       wr        :   in std_logic;
       addr      :   in std_logic_vector(lines-1 downto 0);
       DBUS      :   inout std_logic_vector(wdh-1 downto 0);
       ack       :   out std_logic
    );
end entity;

architecture behaviour of mem is
	type ram_type is array (0 to size-1) of 
      		std_logic_vector(wdh-1 downto 0);
	signal ram_mem: ram_type;
	--signal d_tmp : std_logic_vector(wdh-1 downto 0);
	signal ack_tmp : std_logic;
	
begin
	process (clk)
	begin
		if (clk'event and std_match(clk, '1')) then
		   if (std_match(ack_tmp, '1')) then
		       ack <= '0' after ctd;
		       ack_tmp <= '0' after ctd;
		    else
		       --ack <= ack;
		       ack_tmp <= ack_tmp;
		    end if;
			if (std_match(rd, '1') and std_match(wr, '0')) then
				DBUS <= ram_mem(conv_integer(addr));
				ack <= '1';
				ack_tmp <= '1';
			--	ack <= '0' after ctd;
         elsif (std_match(wr, '1') and std_match(rd, '0')) then
				ram_mem(conv_integer(addr)) <= DBUS;
				ack <= '1';
				ack_tmp <= '1';
     --		    	ack <= '0' after ctd;				
			elsif (std_match(rd, '1') and std_match(wr, '1')) then
			    DBUS <= (DBUS'range => 'Z');
      		 else
             DBUS <= (DBUS'range => 'Z');
         end if;
			if (std_match(rst, '1')) then
			    ack <= '0';
			    ram_mem <=  (
			                 0   => "1000110001100000", -- LOAD R6, #1010101010101010b
			                 1   => "1010101010101010", -- 1010101010101010b
			                 2   => "0010101000000000", -- RTI
			                 
			                 8   => "1000110011100000", -- LOAD R14, #9
			                 9   => "0000000000001001", -- 9
			                 10  => "0001000111100001", -- SUB R14, R1
			                 11  => "1000110000000000", -- LOAD R0, #11..1b
			                 12  => "1111111111111111", -- 11..1b
			                 13  => "0010101000000000", -- RTI
			                 
			                 16  => "0000100000010000", -- LOAD R1, [255]  (R1 = 8)
			                 17  => "0000000011111111", -- 255
			                 18  => "0000100100101111", -- LOAD R2, [R15]  (R2 = 3)
			                 19  => "0001000000010010", -- ADD R1, R2      (R1 = 11)
			                 20  => "0000101000010000", -- PUSH R1
			                 21  => "0000100010000000", -- LOAD R8, [257]
			                 22  => "0000000100000001", -- 257 
			                 23  => "0010100011111111", -- CALL [100]
			                 24  => "0000000001100100", -- 100
			                 25  => "0000101100110000", -- POP R3  (R3 = 15) ends at 2600ns
			                 26  => "0001011000110010", -- CMP R3, R2
			                 27  => "1000101010110001", -- STORE [R11], R1
			                 28  => "0000100101001011", -- LOAD R4, [R11]  (R11 = 300) ends at 3200ns
			                 29  => "1000100100100000", -- STORE [301], R2
			                 30  => "0000000100101101", -- 301
			                 31  => "0000100011000000", -- LOAD R12, [301]
			                 32  => "0000000100101101", -- 301   ends at 3800ns
			                 33  => "1000101110110010", -- STORE [R11, R2], #240
			                 34  => "0000000011110000", -- 240
			                 35  => "1111111111111111", -- ILLEGAL INSTRUCTION
			                 36  => "0000100001010000", -- LOAD R5, [303]  ends at 4400ns
			                 37  => "0000000100101111", -- 303
			                 38  => "1000100010110010", -- LOAD R11, [R11, R2]  ends at 4600ns
			                 39  => "1000110010110000", -- LOAD R11, #300 ends at 4800ns
			                 40  => "0000000100101100", -- 300
			                 41  => "0100000000010001", --- MOVRL R1, R1
			                 42  => "0010000100000000", -- JNZ #64
			                 43  => "0000000001000000", -- 64
			                 44  => "1000110011010000", -- LOAD R13, #1010101010101010b  ends at 5200ns 
			                 45  => "1010101010101010", -- 1010101010101010b
			                 46  => "1111111111111111", -- ILLEGAL INSTRUCTION
			                 
			                 64  => "1000110011010000", -- LOAD R13, #1111000011110000b  ends at 5300ns
			                 65  => "1111000011110000", -- 1111000011110000b
			                 66  => "1111111111111111", -- ILLEGAL INSTRUCTION
			                 
			                 100 => "0000101000010000", -- PUSH R1 (R1 = 11)
			                 101 => "0000110010000000", -- PUSHD R8, #3 (R8 = 15)
			                 102 => "0000000000000011", -- 3
			                 103 => "0000110110100000", -- POPD R10, #3
			                 104 => "0000000000000011", -- 3
      			                 105 => "0000101110010000", -- POP R9   (R9 = 11) ends at 
      			                 106 => "0010100100000000", -- RET #0
      			                 107 => "0000000000000000", -- 0
			                 
			                 255 => "0000000000001000", -- 8
			                 256 => "0000000000000011", -- 3
			                 257 => "0000000000001111", -- 15
			                 
                  		 	    others => "0000000000000000"
                		 	    );
		 	else
		 	
		 	end if;  
          
  
	   end if;
	end process;


end architecture;