[vlsi-nastava:2003] - pitalica by "Zarko Acimovic" <zareac@galeb.etf.bg.ac.yu>

Da li bi neko  mogao da mi objasni zasto  su  a i b u prvom primeru identicni, a u drugom komplementarni?

Prvi primer:

library ieee;
use ieee.std_logic_1164.all;

entity Test is
 port(a: in std_logic; e: out std_logic);
end Test;

architecture Test1 of Test is
  signal connect: std_logic;
begin
  barel: process is
  begin
   connect<=a;
   wait on a;
 end process barel;
 
 memo: process is
 begin
  e<=connect;
  wait on connect;
 end process memo;
 
end Test1;



Drugi primer:

library ieee;
use ieee.std_logic_1164.all;

entity Test is
 port(a: in std_logic; e: out std_logic);
end Test;

architecture Test2 of Test is
 signal connect: std_logic;
begin
 barel: process is
 begin
   connect<=a;
   wait on a;
 end process barel;
 
 memo: process is
 begin
   e<=connect;
   wait on a;
 end process memo;
 
end Test1;