visoka impedansa
Kako da izlazni signal postavimo u stanje visoke impedanse. Receno mi je da
moze sa 'z' ali se to ne moze iskompajlirati. Npr
int_data_out <= (others => 'z');
prijavljuje greske:
Error: COMP96_0077: data_bus_buffer.vhd : (31, 29): Assignment target
incompatible with right side. Expected type "std_ulogic".
Error: COMP96_0079: data_bus_buffer.vhd : (31, 19): Invalid aggregate.
Error: COMP96_0104: data_bus_buffer.vhd : (31, 19): Undefined type of
expression.
pozdrav
Ivan
moze sa 'z' ali se to ne moze iskompajlirati. Npr
int_data_out <= (others => 'z');
prijavljuje greske:
Error: COMP96_0077: data_bus_buffer.vhd : (31, 29): Assignment target
incompatible with right side. Expected type "std_ulogic".
Error: COMP96_0079: data_bus_buffer.vhd : (31, 19): Invalid aggregate.
Error: COMP96_0104: data_bus_buffer.vhd : (31, 19): Undefined type of
expression.
pozdrav
Ivan
- References:
- Re: Bugg u AHDLU 3.5
- From: Nenad Rogulja <nenadrogulja@yahoo.co.uk>
- Re: Bugg u AHDLU 3.5
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