[vlsi-nastava:2004] - Synplify by Milos Milovanovic <miloshm@yahoo.com>

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Synplify

by Milos Milovanovic
utorak, 17. avgust 2004 - 18:06.

Da li neko zna sta sve ne sme da se koristi u VHDL da
bi moglo da se sintetise u Synplify-u?

Unapred hvala,

Milos

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