[vlsi-nastava:2007] - Re: synplify greska by Rade Martinovic <rocky303@gmail.com>

Hello masa,

Friday, January 26, 2007, 4:27:55 PM, you wrote:

> prijavljuje mi gresku "the logic for int_empty does not match standard flip
> flop". prosao je sve ostale provere, kompajliranja. imam i 100tinak
> warnings-a, pominju se neke combinational loop. ne znam kako da resim ovaj
> problem, posto mi i test benc radi. rec je o fifo-u

U synplify-u kada generise gresku imas opciju da za vec broj vrsta
gresaka kliknes na kod grese i vidis njen opis u helpu i kako je
ispraviti. Dakle, ako imas kod greske plavo podvucen, klikni na njega,
pa pokusaj da se snadjes.

Da bih ti ustedeo muke, evo copy/paste-a iz Synplicity helpa:

> @E: The logic for <dout_3> does not match a standard flip-flop
> VHDL/Verilog Compiler Error CL123 
> Description: 
> This error occurs when the HDL code cannot infer a standard flip-flop. The compiler only extracts standard flip-flops that are clocked by a single clock edge. Any attempt to create a register that does not represent a standard flip-flop results in the above error. 
> VHDL Test Case 
> In the following test case, the process is executed whenever there are multiple edges (on clock or on reset), but on both edges, the flip-flop is to be loaded with the current data. This action does not match the normal operation of a flip-flop which causes the compiler to error out with the above message. 
> library ieee;
> use ieee.std_logic_1164.all;
> use ieee.std_logic_arith.all; 
>  
> entity error is
>    port (clk,a,en,rst: in std_logic;
>          dout: out std_logic);
> end error; 
>  
> architecture behave of error is
> begin
>    process (clk,rst) 
>    begin
>       if (rst = '0') then
>          dout <= '0';
>          if (clk ='1' and clk'event) then
>             if ( en = '1' and en'event) then 
>                dout <= a;
>             end if;
>          end if;
>       end if;
>    end process;
> end behave; 
>  
> User Action: 
> Recode the process to match a flip-flop in hardware. To eliminate this error in the above test case, add a condition to reset the flip-flop as shown in the corrected test case below. 
> library ieee;
> use ieee.std_logic_1164.all;
> use ieee.std_logic_arith.all; 
>  
> entity error is
>    port (clk,a,en,rst: in std_logic;
>          dout: out std_logic);
> end error; 
>  
> architecture behave of error is
> begin
>    process (clk,rst) 
>    begin
>       if (rst = '0') then
>          dout <= '0';
>       elsif (clk ='1' and clk'event) then
>          if (en = '1') then
>             dout <= a;
>          end if;
>       end if;
>    end process;
> end behave;


-- 
Best regards,
 Rade                            mailto:rocky303@gmail.com