[vlsi-nastava:2004] - knjiga iz Veriloga by Srdjan Zivojinovic <zevs@tesla.rcub.bg.ac.yu>

http://tesla.rcub.bg.ac.yu/~zevs/knjiga.zip

sa ovog linka mozete skinuti sledecu knjigu (fajl ima 1.6MB)

Verilog HDL: A Guide to Digital Design and Synthesis, Second Edition 
By Samir Palnitkar 
   
Publisher : Prentice Hall PTR 
Pub Date : February 21, 2003 
ISBN : 0-13-044911-3 
Pages : 496 




Written for both experienced and new users, this book gives you broad coverage of Verilog HDL. The
book stresses the practical design and verification perspective ofVerilog rather than emphasizing
only the language aspects. The informationpresented is fully compliant with the IEEE 1364-2001
Verilog HDL standard.


Describes state-of-the-art verification methodologies

Provides full coverage of gate, dataflow (RTL), behavioral and switch modeling

Introduces you to the Programming Language Interface (PLI)

Describes logic synthesis methodologies

Explains timing and delay simulation

Discusses user-defined primitives

Offers many practical modeling tips


Includes over 300 illustrations, examples, and exercises, and a Verilog resource list.Learning
objectives and summaries are provided for each chapter.