[vlsi-nastava:2004] - warning u Sinplify-ju by <atza@tesla.rcub.bg.ac.yu>

Da li neko zna sta bi mogao da bude razlog sledecim upozorenjima:

Latch generated from process for signal empty, probably caused by a
missing assignment in an if or case stmt

Feedback mux created for signal emptysig. Did you forget the set/reset
assignment for this signal?

Trying to extract state machine for register korak

Clock on register transmitready is tied to a constant

Ono sto Sinplify predlaze obicno nema neke vidljive veze sa kodom.

Da li ovo moze imati neke ozbiljne posledice (kasnije greske u uklapanju
svih modula, smanjivanje broja bodova na odbrani domaceg....)?

Pozdrav,
Aca