[vlsi-nastava:2004] - Re: Re: problem sa sintezom by "Ana Balevic" <taucet@eunet.yu>

mislim i da tako nesto takodje nije htelo da prodje. Medjutim napravila sam
novi receiver,koji prodje i simulaciju i sintezu (neverovatno,zar ne ;))
,mada ima dosta warninga. Mislim da ovi sa latchevima ne prave problem-tom
registru dodeljujem vrednost svuda gde treba da se promeni vrednost, ali mi
je taj sa kombinacionom petljom sumnjiv, jer mi kod deluje skroz ok. Ako
neko ume ovo da rastumaci neka javi :)
mogu da posaljem i ceo log fajl.
@W:"C:\My Designs\UART\src\receiver5.vhd":43:1:43:4|Latch generated from
process for signal samplingreg(0), probably caused by a missing assignment
in an if or case stmt
@W:"C:\My Designs\UART\src\receiver5.vhd":43:1:43:4|Found combinational loop
at samplecnt[30]

Warning: Found 1 combinational loops!
         Each loop is reported with an instance in the loop
         and nets connected to that instance.
@W:"c:\my designs\uart\src\receiver5.vhd":76:9:76:22|Found combinational
loop during mapping
1) instance Receive_un26_samplecnt
work.Receiver(rxbeh2)-Receive_un26_samplecnt, output net
work.Receiver(rxbeh2)-Receive_un26_samplecnt
    input nets to instance:
 net work.Receiver(rxbeh2)-samplecnt[0]
 net work.Receiver(rxbeh2)-samplecnt[1]
 net work.Receiver(rxbeh2)-samplecnt[2]
 net work.Receiver(rxbeh2)-samplecnt[3]
 net work.Receiver(rxbeh2)-un1_samplecnt[0]
 net work.Receiver(rxbeh2)-un1_samplecnt[1]
 net work.Receiver(rxbeh2)-un1_samplecnt[2]
 net work.Receiver(rxbeh2)-un1_samplecnt[3]
 net work.Receiver(rxbeh2)-un1_samplecnt[4]
 net work.Receiver(rxbeh2)-un1_samplecnt[5]
 net work.Receiver(rxbeh2)-un1_samplecnt[6]
 net work.Receiver(rxbeh2)-un1_samplecnt[7]
 net work.Receiver(rxbeh2)-un1_samplecnt[8]
 net work.Receiver(rxbeh2)-un1_samplecnt[9]
 net work.Receiver(rxbeh2)-un1_samplecnt[10]
 net work.Receiver(rxbeh2)-un1_samplecnt[11]
 net work.Receiver(rxbeh2)-un1_samplecnt[12]
 net work.Receiver(rxbeh2)-un1_samplecnt[13]
 net work.Receiver(rxbeh2)-un1_samplecnt[14]
 net work.Receiver(rxbeh2)-un1_samplecnt[15]
 net work.Receiver(rxbeh2)-un1_samplecnt[16]
 net work.Receiver(rxbeh2)-un1_samplecnt[17]
 net work.Receiver(rxbeh2)-un1_samplecnt[18]
 net work.Receiver(rxbeh2)-un1_samplecnt[19]
 net work.Receiver(rxbeh2)-un1_samplecnt[20]
 net work.Receiver(rxbeh2)-un1_samplecnt[21]
 net work.Receiver(rxbeh2)-un1_samplecnt[22]
 net work.Receiver(rxbeh2)-un1_samplecnt[23]
 net work.Receiver(rxbeh2)-un1_samplecnt[24]
 net work.Receiver(rxbeh2)-un1_samplecnt[25]
 net work.Receiver(rxbeh2)-un1_samplecnt[26]
End of loops






----- Original Message -----
From: "Vlada" <chiko@yubc.net>
To: <vlsi-nastava@titan.etf.bg.ac.yu>
Sent: Sunday, January 18, 2004 5:38 AM
Subject: Re: [vlsi-nastava] Re: problem sa sintezom


>
> > Uf nesto me zeza The Bat.Dakle evo tog dela:
> >
> > Startuj: process(RxD,current_state) is
> > begin
> >    if RxD='0' and RxD'event then
> >         case current_state is
> >                         when READY => StartFlag<='1';
> >                         when others => StartFlag<='0';
> >                 end case;
> >         else StartFlag<='0';
> >         end if;
> > end process Startuj;
> >
> > ovo je taj proces koji nece da sintetizuje.
> > meni treba da postavim StartFlag na 1 samo kada se state masina nalazi
> > u  stanju READY,a u svim ostalim treba da bude 0. Probala sam da
> > okrenem da prvo udje u case, a u when READY da proverava RxD medjutim
> > ni tako ne radi.
> >
>
> Zasto ovaj uslov ne napises ovako
>
> Startuj: process(RxD,current_state) is
>  begin
>     if RxD='0' and RxD'event and current_state=READY then
>         StartFlag<='1'
>         else StartFlag<='0';
>     end if;
>  end process Startuj;
>
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