problem
Imam jedan problem: uredjaj ima ulaz CLK_I i izlaz CLK_O. Ako napisem u
arhitekturi (ali van procesa) CLK_O <= CLK_I dobijam da: ako je CLK_I = 0,
onda je i CLK_O = 0, ali ako je CLK_I = 1, onda je CLK_O = X !!?!! Pomoc,
molim vas!
arhitekturi (ali van procesa) CLK_O <= CLK_I dobijam da: ako je CLK_I = 0,
onda je i CLK_O = 0, ali ako je CLK_I = 1, onda je CLK_O = X !!?!! Pomoc,
molim vas!
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- From: Marko Misic <enjoysarma@yahoo.com>
- Re: problem CLK_(I/O)
- From: Vladimir Kovacevic <vladak@madnet.co.yu>
- Ciklusi na WB magistrali
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