[vlsi-nastava:2007] - Re: pitanje za asistenta by "Igor Stojkovic" <stojkovic.igor@gmail.com>

On 1/29/07, Rade Jakovljević <radegm@gmail.com> wrote:
> Pazi, ne shvatas jedan detalj. Kad se kaze: "All signals are REGISTERED at
> rising edge of CLK_I...", to ne postavlja nikakva eksplicitna ogranicenja
> sto se tice vremena postavke signala ACK_O, to pravilo jedino kaze da:
> "MASTER CE TAJ SIGNAL CITATI NA NEKU UZLAZNU IVICU". Registered ne znaci
> postavljati signal nego ocitati ga.
>
> Dalje: dijagrami ciklusa i objasnjenja uz njih govore da MASTER po
> pokretanju ciklusa ceka na postavljanje ACK_O (primetiti da i tamo pise da
> on to proverava na uzlaznim ivicama takta), kad REGISTRUJE ACK_O(ACK_I)
> signal onda on podrazumeva da su podaci na linijama DAT_O (ako je read) i
> cita ih, ili da je upis obavljen (write) pa moze da ukine adrese, podatke,
> STB_O,CYC_O signale...
>
> Ove dva prethodna objasnjenja govore da nema nikakvih problema pri
> postavljanju ACK_O signala na silaznu ivicu. Potrebno je samo obezbediti da
> na prvu sledecu UZLAZNU master moze da smatra da je SLAVE odradio posao
> (postavio podatke na DAT_O - read, upisao podatke - write), a ispravno ce
> smatrati samo ako je to stvarno uradjeno.

Izgleda da ste bili u pravu sto se tice ranijeg postavljanja ACK_O:

Although I have really not used this specific core from other bus
timings I have worked with I could definitely say that the output by
saying is registered on the rising edge od CLK_I means that the output
of xx module has to be stable atleast a setup time before the rising
edge of CLK_I so that anything that it is feeding it to (meaning all
modules that receive these signals from the xx module) can use a
register clocked on CLK_I to capture it. So if you are latching on the
falling edge of CLK_I any of your outputs you should be fine as you have
about half a cycle for both setup and hold times. Also note that if you
say your output is available and stable on rising edge of a clock then
you cannot use a register that is clocked by the rising edge of clock to
hold the output data for you. This is because there is going to be a
CLK to Q delay for the flip-flop and after the data starts changing at
the Q pin it also might have to a drive a huge load if it connected to a
bus (the logical fanout of the pin and the capacitance of the routing
metal wire of the bus itself which is huge in case of large chips) which
adds further delay. Hope that helps.
-Ranga
jimyiigor@y... wrote:
> Hello, I'm from Serbia and I am doing a VLSI project for school and my
> collegues and I can't figure something out. Question is about rule 4.10:
>
> The clock input [CLK_I] to each IP core MUST coordinate all activities
> for the internal logic within the WISHBONE interface. All WISHBONE
> output signals are registered at the rising edge of [CLK_I]. All WISHBONE
> input signals must be stable before the rising edge of [CLK_I].
>
> We can't agree on word 'registered'. For example some of as says that
> ACK_O signal of a slave can be set on falling edge of CLK_I so that
> master can detect it on next rising edge. But does this sentence : "All
> WISHBONE output signals are registered at the rising edge of [CLK_I]"
> means that we can only set ACK_O on rising edge of CLK_I or it means
> something else?
>
> We really need an experts opinion on this. Thank you.
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/cores

--
Pozdrav,
Igor Stojkovic mailto: stojkovic.igor@gmail.com